As the size of image display devices has increased in recent years, there has been an increasing demand for flat display devices that use their flat-type plasma display panels to provide large display screens. In a plasma display panel for a television, for example, discharge cells are provided between vertical arrays of electrodes and lateral arrays of electrodes, and images are formed by turning on/off the discharge cells for gas discharge at intersections of the electrodes corresponding to selected display pixels.
FIG. 5 is a schematic block diagram showing a peripheral portion for driving the plasma display panel. In FIG. 5, the plasma display panel 10 includes X electrodes 12 and Y electrodes 14 that are alternately arranged in parallel with each other to extend in the horizontal direction. The X electrodes 12 are connected to each other at one end to provide a common electrode, and the Y electrodes 14 are individually controlled independently of each other. The plasma display panel 10 further includes address electrodes 16 that extend in the vertical direction, i.e., perpendicular to the X electrodes 12 and Y electrodes 14. The X electrodes 12 of the plasma display panel 10 are connected to an X-side common driver 18, and the Y electrodes 14 are connected to a Y scanning driver 20, which is in turn connected to a Y-side common driver 22 for controlling the Y electrodes 14 via the Y scanning driver 20. The addressing electrodes 16 of the plasma display panel 10 are connected to an addressing driver 24.
When displaying one field of image on the plasma display panel 10 constructed as described above, the respective drivers 18, 20, 22, 24 drive the corresponding electrodes 12, 14, 16 in three modes corresponding to a reset period, addressing period and discharge sustaining period. Initially, in the reset period, the Y-side common driver 22 and X-side common driver 18 alternately apply pulses to all of the Y electrodes 14 and X electrodes 12, to sustain discharge of the discharge cells and thereby perform batch writing, and then the X-side common driver 18 applies erasing pulses only to the X electrodes 12 so as to erase all information stored in all of the discharge cells. In the next addressing period, the X-side common driver 18 and Y scanning driver 20 apply voltage to the X electrodes 12 and all of the Y electrodes 14. In this period, the Y scanning driver 20 successively applies scan pulses to the respective Y electrodes 14. In the meantime, the addressing driver 24 successively applies address pulses to selected address electrodes corresponding to the discharge cells to be turned on. As a result, addressing discharge occurs at the selected discharge cells so that the locations of the selected cells are stored by charge storage. In the subsequent discharge sustaining period, the X-side common driver 18 and Y-side common driver 22 apply sustaining pulses alternately to the X electrodes 12 and Y electrodes 14, to sustain discharge of the discharge cells that have been addressed for discharge so as to maintain the display.
The Y scanning driver 20, which is adapted to independently control the respective Y electrodes 14, is constituted by an integrated circuit on which output circuits for driving the respective electrodes are integrated. Each of the output circuits includes a device that functions to charge and discharge one of the Y electrodes 14 during the addressing period, and a device that functions to cause the Y-side common driver 22 to charge and discharge all of the Y electrodes 14 during the reset period and discharge sustaining period. With regard to drive current flowing through the respective devices, current of about 100 mA flows through the device for driving each of the Y electrodes 14 during the addressing period, and current as large as about 400 mA flows through the device for driving all of the Y electrodes 14 during the reset period and discharge sustaining period. To produce the integrated circuit including such devices, a mask is designed to provide a pattern configuration as shown in FIG. 6, and a chip having a cross section as shown in FIG. 7 is produced based on the pattern configuration of FIG. 6, for example.
FIG. 6 is a view showing an example of the pattern configuration of the output circuit for one output, and FIG. 7 is a view showing the cross section of the chip of the output circuit for one output. In these figures, charging device 30 and discharging device 32 used during the addressing period, charging diode 34 and discharging diode 36 used during the reset period and discharge sustaining period, and an electrode portion 38 on the chip are arranged in one row, to thus constitute the output circuit for one output. In practice, a plurality of similar output circuits are arranged in parallel with the output circuit having the above-described configuration.
As shown in FIG. 7, wiring is patterned on the devices formed in a substrate with an interlayer insulating film 42 interposed between the devices and the patterned wiring, such that terminals of the respective devices (portions indicated by small back rectangles in FIG. 6) are connected to each other, and also connected to the corresponding devices of the other output circuits. In the resulting wiring patterning are formed a wire 44 as a power supply line commonly connected to the charging devices 30 of the respective output circuits, a wire 46 as a ground line commonly connected to the discharge devices 32 of the output circuits, and wires 48, 50 as lines through which the charging diodes 34 and discharging diodes 36 of the output circuits are commonly connected to the Y-side common driver 22. Further, a wire 54 serving as an output line of the output circuit is formed on an interlayer insulating film 52 over the interlayer insulating film 42, such that the wire 54 is protected by a protective film 56 except its portion corresponding to the electrode portion 38.
Generally, the electrode portion 38 is located at the closest position to a scribe line along which individual chips are cut from a wafer, so that wire bonding can be conduced with a reduced distance between the electrode portion 38 and a lead. The charging diode 34 and discharging diode 36 that handle large current are located close to this electrode portion 38, so that the patterned wiring for the large current can be shortened.
In the conventional pattern configuration of the output circuit for driving one of scanning electrodes of the plasma display panel, the two devices through which the current flows most during the reset period and discharge sustaining period are arranged in alignment with the electrode portion located closest to the scribe line. Therefore, the wire extending between one of the two diodes and the electrode portion becomes longer than that extending between the other diode and the electrode portion. Also, these wires intersect with the wires commonly connected to the Y-side common driver. Since the height of the wires for the large current is limited at the intersecting locations, the areas of wires and through-holes are inevitably increased in the pattern, resulting in an increase in the chip size. This may affect characteristics of the chip, and increase the cost of the chip.